1. Technical Field
This invention relates in general to computer system architecture and packaging and in particular to an apparatus and method for optimizing computer system packaging.
2. Background Art
Computer processor architectures featuring a 64-bit instruction set incorporate advanced techniques such as explicit parallelism, predication and speculation. These techniques enable a much higher degree of instruction-level parallelism and enable some processors to execute more instructions per clock cycle to deliver superior performance relative to current out-of-order based RISC processors.
Unfortunately, computer systems which utilize these architectures have been very difficult to design due to the high performance, power and thermal requirements of the processors and memory controller chipsets. The systems demand a very high performance memory and IO subsystem which increases the memory controller power dissipation such that the memory controller chipset power dissipation is expected to exceed the power dissipation of the highest performance microprocessors. In addition, the bandwidth requirements of some processors requires pincount intensive memory controller chipset implementations, especially for systems such as 8-way symmetric multiprocessor systems. High pincount chipsets typically require multiple chips to create the memory controller. One problem with partitioning memory control functions is that each chip consumes enormous amounts of power and requires advanced thermal solutions to keep the individual chips running at reliable junction temperatures. Moreover, other support components such as clock drivers, IO bridges and memory subsystems, are also running with higher power dissipation, thus creating a very difficult thermal challenge at the system level. Finally, many processors are placing extremely tight physical constraints on the system planar layout, leaving very little room for the memory controller chipset and supporting logic.
Due to these factors, the multiple chips are required to be as close to one another as possible while still allowing room for their respective heatsink attachments. The spacing limitations do not allow adequate airflow for cooling the chips and other components. The heatsink attachments are typically so large that the separation between the chips negatively affects the electrical symmetry of the system.
Thus, in the prior art, most systems utilize a cooling methodology of spreading the memory controller chipset so that they are either not in line with each other with respect to the direction of airflow in the enclosure, or if they must be in line, that the spacing of the chips, the heatsink size and the airflow requirements are increased to reduce the downstream component's preheated air temperature. This adds to the cost of the system and also makes the design more difficult to implement from a signal timing standpoint, given the increased physical separation of the components. These limitations are particularly problematic since some of these systems cannot withstand further component separation, increased heatsink size or increased airflow.